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--- start [2026/05/29 19:57] – copied beckmanf
+++ start [2026/07/01 14:48] (current) – [Material] slides add name beckmanf
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-===== Master VLSI ======
+====== Master VLSI ======
-Master VLSI - From RTL to GDSII
+The master VLSI course covers the following topics
+  * An introduction to VHDL as digital hardware description language on Register-Transfer-Level.
+  * Simulation based verification on RTL level using GHDL.
+  * An overview of FPGA technology as reconfigurable hardware.
+  * Synthesis for FPGA targets using the Altera DE1 board with a Cyclone II FPGA
+  * Intel/Altera Quartus II software for synthesis
+  * Lab measurements with the FPGA boards
+  * An overview of (digital) CMOS technology and fabrication
+  * Standard Cell based design flow for CMOS with IHP SG13G2 technology
+  * OpenROAD as open source EDA tool
+===== Setup of the EDA environment =====
+You run the EDA experiments on your laptop or PC. We provide a virtual machine for VirtualBox (Windows) or UTM (MacOS) which contains the EDA software for our course.
+How to obtain the virtual machines for VirtualBox and UTM and how to setup the EDA software is described in
+  * [[https://www.hs-augsburg.de/homes/beckmanf/dokuwiki/doku.php?id=ubuntu_virtual_cae_system|THA Virtual CAE System]]
+The software used in the course is
+  * Intel/Altera Quartus II for fpga synthesis
+  * GHDL for VHDL simulation
+  * Codium as editor
+  * Yosys for standard cell synthesis
+  * OpenROAD for Placement, CTS, Routing and Timing Analysis
+  * KLayout for GDSII cell analysis
+and this is all included in the VM.
+===== VHDL and FPGA =====
+{{ :msvlsi-intro.pdf |}}
+{{ ::msvlsi-fpga-intro.pdf |}}
+{{ ::version-management.pdf |}}
+{{ ::toolchain-vhdl-introduction.pdf |}}
+{{ ::vhdl-fundamentals.pdf |}}
+{{ ::concurrent-statements.pdf |}}
+{{ ::synchronous-logic.pdf |}}
+{{ ::fsm-design.pdf |}}
+===== From RTL to GDSII =====
 ==== Material ====
@@ Line 15: / Line 68: @@
 [[https://link.springer.com/book/10.1007/978-3-030-96415-3|Andrew B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2022]]
-[[https://www.ifte.de/books/eda/index.html | VLSI Physical Design - Slides , 2022]]
+[[https://www.ifte.de/books/eda/index.html | Andrew B. Kahng, VLSI Physical Design - Slides, 2022]]
 [[https://safari.ethz.ch/ddca/spring2026/doku.php?id=start | Onur Mutlu, Digital Design and Computer Architecture, ETH Zürich, 2026]]