====== Master VLSI ======

The master VLSI course covers the following topics

  * An introduction to VHDL as digital hardware description language on Register-Transfer-Level.
  * Simulation based verification on RTL level using GHDL.
  * An overview of FPGA technology as reconfigurable hardware.
  * Synthesis for FPGA targets using the Altera DE1 board with a Cyclone II FPGA
  * Intel/Altera Quartus II software for synthesis
  * Lab measurements with the FPGA boards

  * An overview of (digital) CMOS technology and fabrication
  * Standard Cell based design flow for CMOS with IHP SG13G2 technology
  * OpenROAD as open source EDA tool

===== Setup of the EDA environment =====

You run the EDA experiments on your laptop or PC. We provide a virtual machine for VirtualBox (Windows) or UTM (MacOS) which contains the EDA software for our course.

How to obtain the virtual machines for VirtualBox and UTM and how to setup the EDA software is described in

  * [[https://www.hs-augsburg.de/homes/beckmanf/dokuwiki/doku.php?id=ubuntu_virtual_cae_system|THA Virtual CAE System]]

The software used in the course is

  * Intel/Altera Quartus II for fpga synthesis
  * GHDL for VHDL simulation
  * Codium as editor
  * Yosys for standard cell synthesis
  * OpenROAD for Placement, CTS, Routing and Timing Analysis
  * KLayout for GDSII cell analysis

and this is all included in the VM.

===== VHDL and FPGA =====

{{ :msvlsi-intro.pdf |}}

{{ ::msvlsi-fpga-intro.pdf |}}

{{ ::version-management.pdf |}}

{{ ::toolchain-vhdl-introduction.pdf |}}

{{ ::vhdl-fundamentals.pdf |}}

{{ ::concurrent-statements.pdf |}}

{{ ::synchronous-logic.pdf |}}

{{ ::fsm-design.pdf |}}




===== From RTL to GDSII =====

==== Material ====

Course: [[https://github.com/fredowski/Course|https://github.com/fredowski/Course]] (see branch "tha")

OpenROAD flow scripts: [[https://github.com/fredowski/OpenROAD-flow-scripts|https://github.com/fredowski/OpenROAD-flow-scripts]] (see branch "vhdl")

IHP PDK: [[https://github.com/IHP-GmbH/IHP-Open-PDK|https://github.com/IHP-GmbH/IHP-Open-PDK]]

SiliWizz: [[https://tinytapeout.com/siliwiz/introduction/|https://tinytapeout.com/siliwiz/introduction/]]

[[https://link.springer.com/book/10.1007/978-3-030-96415-3|Andrew B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2022]]

[[https://www.ifte.de/books/eda/index.html | Andrew B. Kahng, VLSI Physical Design - Slides, 2022]]

[[https://safari.ethz.ch/ddca/spring2026/doku.php?id=start | Onur Mutlu, Digital Design and Computer Architecture, ETH Zürich, 2026]]

==== Introduction and Overview ====

{{ ::mattvenn-insidecleanroom.mp4 | Youtube: Matt Venn - Inside the Cleanroom }}
[[https://youtu.be/aBDJQ9NYTEU|Youtube: Matt Venn - Inside the Cleanroom at IHP]]

[[https://raw.githubusercontent.com/fredowski/Course/tha/build/c01_lecture.pdf | Chapter 01 pdf]]

==== OpenROAD Flow ====

Video: [[https://youtu.be/DuqdMc4Kc3k|Youtube: "OpenROAD - Turning Designs into Optimized Silicon" - Matt Liberty (Latch-Up 2023)]]

[[https://raw.githubusercontent.com/fredowski/Course/tha/build/c04_lecture.pdf | Chapter 04 pdf]]

==== Process Development Kit (PDK) ====

[[https://raw.githubusercontent.com/fredowski/Course/tha/build/c05_lecture.pdf | Chapter 05 pdf]]

==== Timing Verification / Static Timing Analysis ====

{{ ::msvlsi-timing.pdf | Timing Analysis and Pipelining }}

[[https://www.ifte.de/books/eda/chap8.pdf | Andrew Kahng - Chapter 8 Slides - Timing Closure]]

==== Partitioning / KL Algorithm ====

[[https://www.ifte.de/books/eda/chap2.pdf | Andrew Kahng - Chapter 2 Slides - Partitioning]]

==== Placement ====

[[https://www.ifte.de/books/eda/chap4.pdf | Andrew Kahng - Chapter 4 Slides - Placement]]

OpenROAD uses the RUDY Routing Congestion Estimation based on the following paper:

[[https://ieeexplore.ieee.org/document/4211973 | P. Spindler, F. M. Johannes, Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement, in Design, Automation and Test in Europe Conference 2007, April 2007. DOI: 10.1109/DATE.2007.364463.]]

==== Routing ====

[[https://www.ifte.de/books/eda/chap5.pdf | Andrew Kahng - Chapter 5 Slides - Global Routing]]

[[https://www.ifte.de/books/eda/chap7.pdf | Andrew Kahng - Chapter 7 Slides - Clock Tree Synthesis]]

==== Machine Learning in Chip Design ====

[[https://github.com/FeSens/auto-arch-tournament/blob/main/docs/auto-arch-tournament-blog-post.md | Felipe Sens Bonetto, Apply autoresearch to a RISC-V CPU design, github 2026 ]]

[[https://youtu.be/2A3tiAmaq_c?t=1480 | Youtube: Jeff Dean, Jeff Dean: AI will Reshape Chip Design, NeurIPS 2024 ]]

[[https://arxiv.org/pdf/2302.11014 | Chung-Kuan Cheng, Andrew B. Kahng, et al., "An Updated Assessment of Reinforcement Learning for Macro Placement", arxiv.org, March 2026 ]]