Table of Contents

Master VLSI

Master VLSI

The master VLSI course covers the following topics

An introduction to VHDL as digital hardware description language on Register-Transfer-Level.
Simulation based verification on RTL level using GHDL.
An overview of FPGA technology as reconfigurable hardware.
Synthesis for FPGA targets using the Altera DE1 board with a Cyclone II FPGA
Intel/Altera Quartus II software for synthesis
Lab measurements with the FPGA boards

An overview of (digital) CMOS technology and fabrication
Standard Cell based design flow for CMOS with IHP SG13G2 technology
OpenROAD as open source EDA tool

Setup of the EDA environment

You run the EDA experiments on your laptop or PC. We provide a virtual machine for VirtualBox (Windows) or UTM (MacOS) which contains the EDA software for our course.

How to obtain the virtual machines for VirtualBox and UTM and how to setup the EDA software is described in

THA Virtual CAE System

The software used in the course is

Intel/Altera Quartus II for fpga synthesis
GHDL for VHDL simulation
Codium as editor
Yosys for standard cell synthesis
OpenROAD for Placement, CTS, Routing and Timing Analysis
KLayout for GDSII cell analysis

and this is all included in the VM.

VHDL and FPGA

msvlsi-intro.pdf

msvlsi-fpga-intro.pdf

version-management.pdf

toolchain-vhdl-introduction.pdf

vhdl-fundamentals.pdf

concurrent-statements.pdf

synchronous-logic.pdf

From RTL to GDSII

Material

Course: https://github.com/fredowski/Course (see branch “tha”)

OpenROAD flow scripts: https://github.com/fredowski/OpenROAD-flow-scripts (see branch “vhdl”)

IHP PDK: https://github.com/IHP-GmbH/IHP-Open-PDK

SiliWizz: https://tinytapeout.com/siliwiz/introduction/

Andrew B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2022

Andrew B. Kahng, VLSI Physical Design - Slides, 2022

Onur Mutlu, Digital Design and Computer Architecture, ETH Zürich, 2026

Introduction and Overview

Youtube: Matt Venn - Inside the Cleanroom at IHP

OpenROAD Flow

Video: Youtube: "OpenROAD - Turning Designs into Optimized Silicon" - Matt Liberty (Latch-Up 2023)

Process Development Kit (PDK)

Timing Verification / Static Timing Analysis

Timing Analysis and Pipelining

Andrew Kahng - Chapter 8 Slides - Timing Closure

Partitioning / KL Algorithm

Andrew Kahng - Chapter 2 Slides - Partitioning

Placement

Andrew Kahng - Chapter 4 Slides - Placement

OpenROAD uses the RUDY Routing Congestion Estimation based on the following paper:

P. Spindler, F. M. Johannes, Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement, in Design, Automation and Test in Europe Conference 2007, April 2007. DOI: 10.1109/DATE.2007.364463.

Routing

Andrew Kahng - Chapter 5 Slides - Global Routing

Andrew Kahng - Chapter 7 Slides - Clock Tree Synthesis

Machine Learning in Chip Design

Felipe Sens Bonetto, Apply autoresearch to a RISC-V CPU design, github 2026

Youtube: Jeff Dean, Jeff Dean: AI will Reshape Chip Design, NeurIPS 2024

Chung-Kuan Cheng, Andrew B. Kahng, et al., "An Updated Assessment of Reinforcement Learning for Macro Placement", arxiv.org, March 2026