This is an old revision of the document!
Table of Contents
Master VLSI
The master VLSI course covers the following topics
- An introduction to VHDL as digital hardware description language on Register-Transfer-Level.
- Simulation based verification on RTL level using GHDL.
- An overview of FPGA technology as reconfigurable hardware.
- Synthesis for FPGA targets using the Altera DE1 board with a Cyclone II FPGA
- Intel/Altera Quartus II software for synthesis
- Lab measurements with the FPGA boards
- An overview of (digital) CMOS technology and fabrication
- Standard Cell based design flow for CMOS with IHP SG13G2 technology
- OpenROAD as open source EDA tool
Setup of the EDA environment
You run the EDA experiments on your laptop or PC. We provide a virtual machine for VirtualBox (Windows) or UTM (MacOS) which contains the EDA software for our course.
How to obtain the virtual machines for VirtualBox and UTM and how to setup the EDA software is described in
The software used in the course is
- Intel/Altera Quartus II for fpga synthesis
- GHDL for VHDL simulation
- Codium as editor
- Yosys for standard cell synthesis
- OpenROAD for Placement, CTS, Routing and Timing Analysis
- KLayout for GDSII cell analysis
and this is all included in the VM.
VHDL and FPGA
From RTL to GDSII
Material
Course: https://github.com/fredowski/Course (see branch “tha”)
OpenROAD flow scripts: https://github.com/fredowski/OpenROAD-flow-scripts (see branch “vhdl”)
IHP PDK: https://github.com/IHP-GmbH/IHP-Open-PDK
SiliWizz: https://tinytapeout.com/siliwiz/introduction/
VLSI Physical Design - Slides , 2022
Onur Mutlu, Digital Design and Computer Architecture, ETH Zürich, 2026
Introduction and Overview
OpenROAD Flow
Process Development Kit (PDK)
Timing Verification / Static Timing Analysis
Partitioning / KL Algorithm
Placement
Andrew Kahng - Chapter 4 Slides - Placement
OpenROAD uses the RUDY Routing Congestion Estimation based on the following paper: